Trench-gate ldmos structures

ABSTRACT

MOSFET devices for RF applications that use a trench-gate in place of the lateral gate conventionally used in lateral MOSFET devices. A trench-gate provides devices with a single, short channel for high frequency gain. Embodiments of the present invention provide devices with an asymmetric oxide in the trench gate, as well as LDD regions that lower the gate-drain capacitance for improved RF performance. Refinements to these TG-LDMOS devices include placing a source-shield conductor below the gate and placing two gates in a trench-gate region. These improve device high-frequency performance by decreasing gate-to-drain capacitance. Further refinements include adding a charge balance region to the LDD region and adding source-to-substrate or drain-to-substrate vias.

CROSS-REFERENCES TO RELATED APPLICATIONS

This application is a continuation application of U.S. patentapplication Ser. No. 12/499,778, filed Jul. 8, 2009, which is adivisional application of U.S. patent application Ser. No. 10/951,259,filed Sep. 26, 2004, now U.S. Pat. No. 7,576,388. U.S. patentapplication Ser. No. 10/951,259, filed Sep. 26, 2004, now U.S. Pat. No.7,576,388, claims priority to and the benefit of U.S. ProvisionalApplication No. 60/506,194, filed Sep. 26, 2003 and is acontinuation-in-part of U.S. patent application Ser. No. 10/269,126,filed Oct. 3, 2002, now U.S. Pat. No. 7,033,891. Each of the disclosuresof the patent applications listed above is incorporated herein byreference in its entirety.

The following patent application is commonly assigned with the presentapplication and is incorporated by reference herein in its entirety:

U.S. patent application Ser. No. 60/405,369, entitled “Improved MOSGating Method for Reduced Miller Capacitance and Switching Losses”,filed Aug. 23, 2002.

BACKGROUND

The invention generally relates to methods for fabricating integratedcircuits (ICs) and semiconductor devices and the resulting structures.More particularly, the invention relates to metal oxidesemiconductor-field-effect transistor (MOSFET) devices and methods formaking such devices. Even more particularly, the invention relates toimprovements that may be made to trench-gate laterally-diffused MOSFETdevices and methods for making such improved devices.

In IC fabrication, devices such as transistors may be formed on asemiconductor wafer or substrate, which is typically made of silicon.MOSFET devices are widely used in numerous electronic apparatus,including automotive electronics, disk drives and power supplies.Generally, these apparatus function as switches and are used to connecta power supply to a load.

One of the applications in which MOSFET devices have been used is forradio frequency (RF) applications. Such RF MOSFET devices are generallylateral transistors. See, for example, the lateral MOSFET devicedescribed in U.S. Pat. No. 5,949,104, as well as the device illustratein FIG. 1. Such lateral MOSFET devices often have a diffused source thatallows a backside contact for improved thermal conducting and reducedparasitics.

Recent advances in lateral (or laterally-diffused) MOSFET (LDMOS)devices have improved the performance and cost characteristics oflateral MOSFET devices when compared to vertical MOSFET devices for RFpower amplifiers in base stations applications. Such RF LDMOS deviceshave been particularly useful for wireless base station applications.The RF vertical (or vertically-diffused) VDMOS structure unfortunatelysuffers from certain limitations relative to the LDMOS such as highoutput capacitance (which decreases efficiency), decreased power gain,narrowing of the usable bandwidth, and source inductance that decreasesthe operating efficiency.

Thus, what is needed are circuits, methods, and apparatus that providean improved LDMOS having reduced output capacitance, increased powergain, and more useable bandwidth.

SUMMARY

Embodiments of the present invention provide MOSFET devices for RFapplications that use a trench-gate in place of the lateral gateconventionally used in lateral MOSFET devices. A trench-gate providesdevices with a single, short channel for high frequency gain.Embodiments of the present invention provide devices with an asymmetricoxide in the trench gate, as well as LDD regions that lower thegate-drain capacitance for improved RF performance. Such features allowthese devices to maintain the advantages of the LDMOS structure such asbetter linearity, thereby increasing the RF power gain. The trench-gateLDMOS (TG-LDMOS) of the invention also reduces the hot carrier effectswhen compared to regular LDMOS devices by reducing the peak electricfield and impact ionization.

Refinements to these TG-LDMOS devices include placing a source-shieldconductor below the gate and placing two gates in a trench-gate region.These improve device high-frequency performance by decreasinggate-to-drain capacitance. Further refinements include adding a chargebalance region to the LDD region and adding source-to-substrate ordrain-to-substrate vias. Various embodiments of the present inventionmay incorporate one or more of these or the other features describedherein.

An exemplary embodiment of the present invention provides a MOSFET. ThisMOSFET includes a first silicon region of a first conductivity type, thefirst silicon region having a surface, and a gate-trench regionextending from the surface of the first silicon region into the firstsilicon region. The gate trench region includes a source-shield regionincluding a first conductive region, and a gate region comprising asecond conductive region and between the surface of the first siliconregion and the source-shield region. The gate-trench region has anasymmetric insulating layer along two of its opposing sidewalls. TheMOSFET further includes a source region including a dopant region of asecond conductivity type, the dopant region laterally extending alongone side of the gate trench region and contacting a source electrode;and a lightly-doped drain region of the second conductivity typelaterally extending below and along an opposing side of the one side ofthe gate trench region and contacting a drain electrode.

Another exemplary embodiment provides another MOSFET. This transistorincludes a first silicon region of a first conductivity type, the firstsilicon region having a surface, a gate-trench region extending from thesurface of the first silicon region into the first silicon region. Thegate trench region includes a first gate region comprising a firstconductive region, a second gate region comprising a second conductiveregion and between the surface of the first silicon region and the firstgate region. The gate-trench region has an asymmetric insulating layeralong two of its opposing sidewalls. This device further includes asource region comprising a dopant region of a second conductivity type,the dopant region laterally extending along one side of the gate trenchregion and contacting a source electrode, and a lightly-doped drainregion of the second conductivity type laterally extending below andalong an opposing side of the one side of the gate trench region andcontacting a drain electrode.

A further exemplary embodiment provides another MOSFET. This transistorincludes a first silicon region of a first conductivity type, the firstsilicon region having a surface, a gate-trench region extending from thesurface of the first silicon region into the first silicon region, thegate trench region including a gate region comprising a conductiveregion. The gate-trench region also including an asymmetric insulatinglayer along two of its opposing sidewalls. The device also includes asource region comprising a dopant region of a second conductivity type,the dopant region laterally extending along one side of the gate trenchregion and contacting a source electrode, and a lightly-doped drainregion of the second conductivity type laterally extending below andalong an opposing side of the one side of the gate trench region andcontacting a drain electrode, the lightly-doped drain region comprisinga charge-balance region of the first conductivity type.

A better understanding of the nature and advantages of the presentinvention may be gained with reference to the following detaileddescription and the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a prior art MOSFET device;

FIG. 2 illustrates a MOSFET device according to an embodiment of thepresent invention;

FIGS. 3-5 illustrate a MOSFET device according to an embodiment of thepresent invention at various processing stages during manufacture;

FIG. 6 illustrates a MOSFET device according to another embodiment ofthe present invention.

FIG. 7 shows a cross section view of a TG-LDMOS having a source shieldintegrated with the gate structure in accordance with an embodiment ofthe present invention;

FIGS. 8A-8D depict an exemplary sequence of process steps formanufacturing the source-shield TG-LDMOS in FIG. 7 in accordance withone embodiment of the present invention;

FIGS. 9A and 9B respectively show a cross section view of a TG-LDMOShaving two control gates and a corresponding transistor symbol inaccordance with another embodiment of the present invention;

FIGS. 10A-10D depict an exemplary sequence of process steps formanufacturing the dual-gate TG-LDMOS in FIG. 9A in accordance with oneembodiment of the present invention;

FIGS. 11A and 11B show cross section views of two TG-LDMOS structureswherein a charge-balancing technique is used to improve the breakdownvoltage in accordance with another embodiment of the present invention;

FIGS. 12A and 12B respectively show a cross section view of TG-LDMOSstructure having a source-substrate via and a variation thereof inaccordance with an embodiment of the present invention;

FIG. 12C shows integration of the source-substrate via of FIG. 12A withthe source shield TG-LDMOS structure of FIG. 7;

FIG. 13A through 13C show a cross section view of TG-LDMOS structures;

FIG. 14 is a cross section view illustrating how the source-substratevia can be advantageously used to obtain a smaller cell pitch;

FIG. 15 is a cross section view showing one technique forinterconnecting the source-shield to the source terminal;

FIG. 16 is a cross section view showing the combination of the dual-gatestructure depicted in FIG. 9A with the source to substrate connectiontechnique depicted in FIG. 12A;

FIG. 17 is a cross section view showing the dual-gate structure of FIG.9A in combination with the charge balance technique of FIG. 11;

FIG. 18 is a cross section view showing a variation of the dual-gatestructure in combination with the charge balance technique of FIG. 11;and

FIG. 19 is a cross section view showing the same variation of thedual-gate structure depicted in FIG. 18 in combination with an n+ drainsinker.

DETAILED DESCRIPTION

The following description provides specific details in order to providea thorough understanding of the invention. The skilled artisan, however,would understand that the invention can be practiced without employingthese specific details. Indeed, the invention can be practiced bymodifying the illustrated system and method and can be used inconjunction with apparatus and techniques conventionally used in theindustry. For example, the MOSFET devices are described for RFapplications, but could be used in non-RF applications such asswitching.

As noted above, the invention generally comprises a structure thatcombines the benefits of the LDMOS structure (i.e., a low gate-to-draincapacitance and a good linearity) with the benefits of a short gatechannel. Thus, any structure that combines theses feature can beemployed in the invention. In one embodiment of the present invention,these benefits are combined by using a trench gate laterally-diffusedMOSFET device as described below. By using this structure, the breakdowncapabilities of conventional LDMOS structure can be improved. Inaddition, the carrier effects (i.e., injection) are improved, and thepeak electric field and impact ionization of the drain region isreduced.

To achieve these benefits, the structure illustrated in the FIG. 2 isused in the invention. In FIG. 2, the MOSFET device 5 comprises asemiconductor substrate 10, typically of monocrystalline silicon (Si),with an epitaxial layer 60 formed thereon. In one embodiment of thepresent invention, the silicon substrate 10 can have a firstconductivity type, such as B (boron), with a dopant concentration ofabout 2×10¹⁹ atoms/cm³. In another embodiment of the present invention,the substrate can have a resistivity ranging from 0.005 to 0.01 ohmcentimeter. A contact region 55 can be located on the “backside” of thesubstrate 10. In one embodiment of the present invention, the contactregion 55 is a metal contact. In one embodiment of the presentinvention, the depth of the epitaxial layer 60 can range from about 3 toabout 9 microns and can have a first conductivity dopant concentrationof about 1.2×10¹⁵ atoms/cm³. In another embodiment of the presentinvention, the epitaxial layer can have a resistivity ranging from about20 to about 30 ohm centimeters.

A gate structure 90 is located between source region 95 and drain region100. The gate structure 90 is separated from the source region 95 by abody region 40. And the gate structure 90 is separated from the drainregion 100 by a lightly doped drain (LDD) region 75.

The gate structure 90 contains gate conductor 30, as well as aninsulating layer 80 surrounding that part of the gate conductor 30 inthe trench 85. The MOSFET device contains channel region 25 of a firstconductivity type (p-type in one embodiment of the present invention)that is adjacent to the side of the insulating layer 80 of the gatestructure 90 nearest the source region 95. Because of this configurationof the gate in the trench 85, the gate structure 90 is often referred toas a trench gate in which length of the gate is controlled by the depthof the trench 85. In one embodiment of the present invention, the trenchdepth can range from about 0.5 to about 4.0 microns. In anotherembodiment of the present invention, the depth of the trench can beabout 1 to about 2 microns. In yet another embodiment of the presentinvention, the trench depth can be about 1.5 microns.

With this configuration of the gate structure 90, the thin insulatinglayer between the channel region 25 and the conducting layer 30 operatesas a high-quality gate insulating layer.

In addition, the insulating layer 80 (which in some embodiments of theinvention is asymmetric) can also reduce the gate to drain capacitance(Cgd). As well, the thick bottom oxide (with a thickness of about 1 kÅto about 4 kÅ) can reduce the gate-to-drain overlap capacitance andthereby lower the gate charge.

By applying a positive gate voltage to device 5, the channel region 25can change the polarity from a first conductivity type to a secondconductivity type. This polarity change—called inversion—permits thecarriers to drift (e.g., flow) from the dopant region 70 to the lightlydoped drain (LDD) region 75. Thus, the channel region 25 can bemodulated by a positive gate voltage.

Source region 95 comprises dopant region 35 and source electrode 15. Thedopant region 35 is typically of a first conductivity type with aconcentration ranging from about 5×10¹⁵ to about 1×10¹⁹ atoms/cm³. Inone embodiment of the present invention, the concentration of dopantregion 35 is about 1×10¹⁹ atoms/cm³. The source electrode 15 is locatedover dopant region 35 and overlaps body region 40. The body region 40 istypically of a first conductivity type with a concentration greater thanor equal to the concentration of the epitaxial layer 60. In oneembodiment of the present invention, the concentration of body region 40is about 2.5×10¹⁵ atoms/cm³.

As known in the art, source electrode 15 can be separated from the bodyregion 40 by dopant region 70 of a second conductivity type. As well,the source electrode 15 can be separated from the gate structure 90 by adistance (a) that depends on the desired characteristics of the gate.Generally, this distance (a) can range from about 0.5 to about 1.5microns.

The drain region 100 contains a drain electrode 20 overlying a portionof LDD region 75. In one embodiment of the present invention, the drainelectrode 20 is separated from the gate by a distance (b) depending onthe desired drain-source breakdown voltage. In one embodiment of thepresent invention, this distance typically can be between about 3 toabout 5 microns. In another embodiment of the present invention, thedrain electrode is separated from gate by a distance of about 4 microns.The drain electrode 20 is also separated from the LDD region 75 by adopant region 65. In one embodiment of the present invention, the dopantregion 65 is of a second conductivity type with a concentration ofranging from about 1×10¹⁵ to 1×10¹⁶ atoms/cm³.

The LDD region 75 contains a first drain drift region 45 of the MOSstructure. The first drain drift region 45 is formed completely withinthe epitaxial layer 60, with a part underlying the trench 85. In oneembodiment of the present invention, the first enhanced drain driftregion 45 has second conductivity type when the epitaxial layer 60 has afirst conductivity type. In one embodiment of the present invention, thefirst enhanced drain drift region 45 can have a dopant concentrationranging from about 1×10¹¹ to about 5×10¹³ atoms/cm³. In anotherembodiment of the present invention, this dopant concentration is about2×10¹² atoms/cm³. The first enhanced drain region 45 can have lateraldimensions ranging from about 0.5 to about 5.0 microns and verticaldimensions ranging from about 0.2 to about 0.5 microns

The LDD region 75 also contains a second enhanced drain drift region 50that is adjacent to and contacting the first drain drift region 45. Thesecond drain drift region 50 is also formed completely within theepitaxial layer 60. In one embodiment of the present invention, thesecond drain drift region 50 has second conductivity type when theepitaxial layer 60 has a first conductivity type. In one embodiment ofthe present invention, the second drain drift region can have a dopantconcentration greater than the first drain drift region 45. In oneembodiment of the present invention, the dopant concentration can rangefrom about 1×10¹¹ to about 1×10¹⁴ atoms/cm³. In another embodiment ofthe present invention, this dopant concentration is about 1×10¹³atoms/cm³. The second drain region 50 can have lateral dimensionsranging from more than 0 to about 5 microns and vertical dimensionssubstantially similar to the first drain drift region 45.

Using the two drain drift regions 45 and 50 in LDD region 75 allows oneto increase the maximum drain drift current density of the device, aswell as increase the drain-to-source breakdown voltage. Indeed, theeffective electrical field in the LDD region 75 is strong enough tocause the avalanche effect of carrier multiplication at certain criticalconcentration of carriers. Thus, the critical carrier concentration canbe related to the breakdown voltage in device 5. In one embodiment ofthe present invention, three or more drift regions that are uniformlygraded from a light dopant concentration to a heavier dopantconcentration can be used as LDD region 75.

In one embodiment of the present invention, the second drain driftregion 50 has a concentration higher than the concentration of the firstdrain drift region 45. This configuration can result in theredistribution of the critical electrical fields in the channel region25 and can result in an increase of the drain-to-source breakdownvoltage. The maximum current density in the source-drain channel of thedevice can also be increased when the total concentration in the draindrift region is increased.

Using the two drain drift regions 45 and 50 also allow the LDD region 75to act as a non-linear resistor, especially when the applied voltage isvaried. This non-linear behavior suggests the existence of a pinch-offpoint in the LDD region 75. In other words, as the applied voltage isincrease, the depletion region present in the LDD region 75 can expandand lead to a pinch-off point.

Configuring the LDD region 75 as indicated above can also be used tosupport efficient operation of device 5. The dopant profile of the LDDregion 75 can be controlled by having different sectors each with adifferent dopant concentration. The different doping concentrations canbe configured to ensure that any breakdown does not occur near the uppersurface of the device, but deeper within the LDD region 75 near theinterface of the dopant region 65 and LDD region 75. The ability toconfigure the LDD region 75 in this manner must be carefully balanced,of course, with the other operating parameters of the device such as Cgdand the drain to source capacitance (Cds).

As noted above, the drift drain region 45 extends under the trench 85.In one embodiment of the present invention, the dopant concentration ofthe region under the trench 85 should be higher than the concentrationof the remainder of LDD region 75. This region is an extension of LDDregion 75 and helps create a current flow from the drain to the source.The concentration of this region should be tailored to the requireddrain-source breakdown voltage, as well as to not to substantiallyincrease the gate to drain capacitance.

By using a trench gate, the devices of the invention are able to achieveseveral improvements over existing LDMOS devices. First, the devices ofthe invention have an improved RF power gain and efficiency due to thereduction of the Cgd resulting from the asymmetric insulating materialin the trench and the shorter channel. Second, the devices of theinvention are able to reduce the hot carrier effects by reducing thepeak electric field. Third, the operating voltages of the devices of theinvention can be increased above the capabilities of existing LDMOSdevices.

The device illustrated in FIG. 2 can be made by any process resulting inthe depicted structure. In one embodiment of the present invention, theprocess described below and illustrated in FIGS. 3-5 is used to make thestructure depicted in FIG. 2.

Referring to FIG. 3, the process begins with substrate 10. Any substrateknown in the art can be used in the invention. Suitable substratesinclude silicon wafers, epitaxial Si layers, polysilicon layers, bondedwafers such as used in silicon-on-insulator (SOI) technologies, and/oramorphous silicon layers, all of which may be doped or undoped. If thesubstrate is undoped, it can then be doped with a first conductivitytype dopant to the concentration noted above by any method known in theart.

Next, the backside contact region 55 is formed. In one embodiment of thepresent invention, the contact region 55 can be formed by ametallization process. Then, if the epitaxial layer 60 is not alreadypresent, it is formed on the substrate 10 by any process known in theart. If the epitaxial layer is not doped in situ, then the desireddoping concentration can be formed using any known process. Next, thevarious dopant regions 35, 40, 45, 50, 65, and 70 can be formed as knownin the art.

As depicted in FIG. 3, trench 85 is then formed in the upper surface ofthe epitaxial layer 60. The trench 85 can be are formed by any suitablemasking and etching process known in the art. For example, the etchingprocess can begin by forming a mask (not shown) with an opening(s) wherethe trench(es) will be formed. The silicon in the trench is then removedby etching through the mask. The parameters of the etching process arecontrolled to preferably form round bottom corners, smooth andcontinuous sidewalls, flat and clean trench bottom surfaces, and trenchdepth, thereby maintaining the integrity of the device characteristicsusing the trenches. After forming the trenches, the mask is removed byany suitable process known in the art.

As depicted in FIG. 4, the trench 85 is then filled with the materialfor insulating layer 80. This material for the insulating layer can beany high-quality insulating material known in the art, such as siliconnitride, silicon oxide, or silicon oxynitride. In one embodiment of thepresent invention, the insulating layer is silicon oxide (or “oxide”).In this embodiment of the present invention, an oxide layer is providedon the top surface of the epitaxial layer 60, including the trench 85.Any suitable method known in the art—including oxidation anddeposition—yielding a high quality oxide layer can be used to providethis oxide layer. The portions of the oxide layer on the surface of theepitaxial layer 60 are then removed by any known process, leaving theoxide solely within the trench 85.

Next, a second trench 105 is formed within the insulating layer 80. Thissecond trench can be formed in a manner substantially similar to themethod used to form the first trench 85, with a few modifications. Thefirst modification is that the mask material and the etching chemicalmay be different to account for the difference between etching siliconand etching the material for the insulating layer 80, e.g., oxide. Thesecond modification is that the width of the mask openings for thesecond trench 105 will be smaller than the first trench 85.

After the second trench 105 is formed, the conductive material 110 forthe gate, source, and drain is deposited to fill and overflow theremaining portions of the second trench 105 as illustrated in FIG. 5.This conductive layer can be suitable material that can be used as agate conductor, such as a metal, metal alloy, or polysilicon. In oneembodiment of the present invention, the conductive layer is heavilydoped polysilicon. The conductive layer can be deposited using any knowndeposition process, including chemical vapor deposition process.Optionally, the conductive layer 105 can be doped with any suitabledopant to the desired concentration, particularly when the conductivelayer is polysilicon or when a silicide can be used to reduce theresistance of the gate. Excess (and unneeded) portions of the conductivelayer 105 are then removed using any conventional process to form thegate conductor 30, the source electrode 15, and the drain electrode 20.In another embodiment of the present invention, additional deposition,masking, and etching steps can be used if the conductive material forthe gate conductor, the source electrode, and the drain electrode willbe different.

After the above processes are concluded, conventional processing cancontinue to finish the MOSFET device. As well, other processing neededto complete other parts of the semiconductor device can then be carriedout, as known in the art.

In the embodiment of the present invention described above andillustrated in the Figures, the first conductivity type is a p-typedopant and the second conductivity type is an n− type dopant. In anotherembodiment of the present invention, the device can be configured withthe first conductivity type being a n-type dopant and the secondconductivity type dopant being a p-type dopant.

The devices of the invention can also be modified to contain more than asingle gate. For example, as depicted in FIG. 6, the devices of theinvention can contain two trench gates between the source and drain. Inthe embodiment of the present invention shown in FIG. 6, the device cancontain one gate with a symmetric oxide and one gate with an asymmetricoxide. In another embodiment of the present invention, both gates cancontain an asymmetric oxide. The device in FIG. 6 is manufacturedsimilar to the device depicted in FIG. 2, except that two trenches withtwo gate structures could be provided instead of a single trench. Othermodifications are described below:

FIG. 7 shows a cross section view of a TG-LDMOS having a source shield710 integrated with the gate structure 720 in accordance with anembodiment of the invention. The source shield is located below the gate730 and is electrically connected (not shown) to the source terminal740. In one embodiment, the connection to the source terminal 740 ismade by extending the source shield 710 in the direction perpendicularto the page and then routing it up to the trench surface whereelectrical contact is made to the source metal 750. Such devices can beused in RF applications and in high power switching applications. Asshown, the TG-LDMOS has a vertical channel but employs a lateral driftregion which together with an n-type region wrapping around a bottomportion of the trench forms a contiguous n-type region. The trench has athick insulator along its bottom and an asymmetrical insulator along itssidewalls (i.e., has a thicker insulator along its drain-side sidewallthan its source-side sidewall) to reduce parasitic capacitance.

The source shield 710 improves device high frequency gain by reducingthe gate-to-drain capacitance (Cgd) and improves the breakdown voltagecharacteristics. While in operation, the electric field resulting fromthe biased gate 730 is terminated in the shield plate (source-shield710) thus minimizing Cgd. There is a slight increase in input or Cisscapacitance due to the presence of the source shield 710 but this can becompensated by input impedance matching. Accordingly, by providing a“shield” between the gate 730 and the drain 760, Cgd is significantlyreduced thus increasing the maximum oscillation frequency. Moreover, thesource shield 710 helps reduce the hot carrier effects by reducing thepeak electric field and impact ionization

The process technology for forming the source-shield TG-LDMOS in FIG. 7is compatible with conventional silicon MOSFET technology. In oneembodiment, the process steps described below and illustrated in FIGS.8A-8D is used to make the source-shield TG-LDMOS in FIG. 7.

A silicon substrate such as silicon wafers or epitaxial silicon layersmay be used. If the substrate is undoped, it can then be doped with afirst conductivity type dopant to a desired concentration by any methodknown in the art. In one embodiment, highly doped silicon wafer is usedto reduce source resistance in the substrate. In FIG. 8A, a p+ typesubstrate 810 is used. If an epitaxial layer is not already present, itis formed on the substrate using conventional methods. If the epitaxiallayer is not doped in situ, then the desired doping concentration may beobtained using conventional methods. As shown in FIG. 8A, the variousdopant regions such as the p+ type sinker 820 and n− type LDD region 830are formed as known in the art. For example, conventional sinker maskimplant and drive-in steps and LDD mask implant and drive-in steps maybe carried out to form the p+ type sinker 820 and n− type LDD regions830, respectively. Other dopant regions such as the p− type body region(not shown) and n+ contact regions (not shown) may also be formed atthis stage even though they are shown being formed in later stages.

A trench 850 is then formed in the upper surface of the epitaxial layerusing conventional masking and etching steps. For example, the etchingprocess can begin by forming an oxide hard mask with an opening wherethe trench 850 is to be formed. The silicon in the trench area 850 isthen removed by etching through the mask opening. The parameters of theetching process are controlled to preferably form rounded corners andsmooth and clean trench sidewalls and bottom surfaces, therebymaintaining the integrity of the device characteristics. In oneembodiment, after the trench surfaces are cleaned, the portion of theLDD region 830 which wraps abound the trench is formed by carrying out aconventional implant (e.g., angled implant) or plasma immersion dopingor equivalent, followed by activation. The oxide hard mask may be thenbe removed or left in place for subsequent processing.

In FIG. 8B, the trench 850 is then filled with insulating material 860.The insulating material can be any high-quality insulating materialknown in the art, such as silicon nitride, silicon dioxide, or siliconoxynitride. In the embodiment shown in FIG. 8B, the insulating layer issilicon dioxide (or “oxide”) which is formed on the top surface of theepitaxial layer and in the trench. Any suitable method known in theart—including oxidation and deposition—yielding a high quality oxidelayer can be used to form this oxide layer. The portions of the oxidelayer on the surface of the epitaxial layer are then removed usingconventional methods (e.g., CMP or etch techniques), thus leaving theoxide solely within the trench.

Using a mask (shown in FIG. 8B as the top layer), a trench 852 is thenformed within and on the source-side of the oxide-filled trench. In oneembodiment, the trench 852 is formed in the oxide by etching the oxidethrough the mask opening. Such etching step would need to be selectiveto oxide over silicon to prevent etching of the silicon along the leftsidewall (source side) if the mask opening overlaps the left edge of thetrench due to for example misalignment. A thermal oxide could then beformed on the exposed silicon sidewall. A conductive material isdeposited to fill the trench and then recessed into the oxide trench toform the “shield electrode” 870. This conductive material may, forexample, be from the same material as the gate conductor, such as ametal, metal alloy, or polysilicon.

In FIG. 8C, conventional oxidation and etch steps are carried out torefill the oxide trench 850. Using a mask (shown in FIG. 8C as the toplayer), the oxide above and to the left of the shield electrode ispartially removed so that a layer of oxide remains over the shieldelectrode and the n− type LDD 830 along the left sidewall (i.e.,source-side) of the trench becomes exposed, as shown. In an alternateembodiment, a selective deposition technique is used to form the oxidelayer over the shield electrode.

In FIG. 8D, a gate oxide layer 880 is formed along the exposed siliconsidewall of the trench using conventional methods. A suitable conductivematerial (e.g., polysilicon) is then deposited and etched back to fromthe gate electrode. Using a mask, implant and drive-in steps areperformed to form the p− type body region 890, as is known in the art.Using source/drain mask, conventional implant and activation steps areperformed to form the n+ type source 892 and drain 894 regions. Thefinal structure shown in FIG. 7 is obtained upon forming dielectric andmetal layers (not shown), including the back metal, using conventionalmethods.

FIG. 9A shows a cross section view of a TG-LDMOS having two controlgates 910 and 920 in accordance with another embodiment of theinvention. A trench structure having dual-gates is disclosed in theabove-referenced patent application entitled “Improved MOS Gating Methodfor Reduced Miller Capacitance and Switching Losses”. However, thedual-gate structure in the above-referenced application is notimplemented in a TG-LDMOS structure and is different from the FIG. 9Astructure in many respects.

In FIG. 9A, both control gates (Gate-1 910 and Gate-2 920) overlap thechannel region 930, and thus both control gates need to be properlybiased to turn on the MOSFET. The top gate (Gate-1) 910 modulates thecurrent flow when the bottom gate (Gate-2) 920 is biased appropriately.The bottom gate 920 can be continuously biased or only biased prior to aswitching event. FIG. 9B shows a transistor symbol of the dual gateTG-LDMOS. The dual-gate technique in FIG. 9A helps reduce the devicegate-to-drain capacitance (Cgd) to extremely low levels which in turnreduces switching losses of any MOS-gated device. Thus, the switchingefficiency is improved allowing operation at higher frequencies. Thedual-gate structure is particularly suitable for use in suchapplications as high voltage RF devices or other high frequencyswitching MOSFETs. In RF MOSFET devices, the lower Cgd is highlydesirable because it increases RF gain and minimizes signal distortion.Also, Gate-2 920 acts much like the shield element 710 in FIG. 7 toshield the dynamic Gate-1 910 although it is biased differently thanthat in FIG. 7.

The process technology for forming the dual-gate TG-LDMOS in FIG. 9A iscompatible with conventional silicon MOSFET technology. In oneembodiment, process steps similar to those depicted in FIGS. 8A-8D withsome modifications in connection with forming the lower gate, whichwould be known to one skilled in the art, may be used. An alternate setof process steps described below and illustrated in FIGS. 10A-10D mayalso be used to make the dual-gate TG-LDMOS in FIG. 9A.

Process steps depicted in FIGS. 10A-10D are similar to those describedabove for TG-LDMOS structure in FIG. 7 except for adjustments in thevertical positions and few other differences. The particular sequence ofsteps described herein is not intended to be limiting, and may bemodified in ways known to one skilled in this art for optimum results.

In FIG. 10A, p− type body region 1010, n− type LDD 1020, and n+ typesource 1030 and drain 1040 regions are formed using conventional mask,implant, and drive-in steps. A first trench and the portion of the LDDregion wrapping around the trench are formed in a manner similar to thatin FIG. 8A.

In FIG. 10B, after filling the first trench with a dielectric material(e.g., oxide) and etching back to the planar surface, a second trench1050 is formed in the silicon next to the dielectric-filled trench. Thisnew trench can be etched conventionally into silicon and is providedwith a thick oxide on the bottom and gate oxide on the sidewall. Thiscan be accomplished using selective oxide deposition, or a LOCOStechnique as disclosed in U.S. Pat. Nos. 6,437,386, 6,368,920, and6,444,528, relevant portions of which are incorporated herein byreference. If the depth of the trench does not extend much below the LDDor body region, then an implant into the trench bottom would suffice tobridge the drain LDD structure to the trench sidewall where the channelwill be formed. A threshold adjustment implant into the left (sourceside) sidewall of the trench may be carried out using an angled implant.This step might be necessary depending on the trench bottom LDD process.

In FIG. 10C, a conformal polysilicon layer 1060 is deposited lining thetrench. A dielectric 1070 is deposited and planarized to fill thepolysilicon-lined trench. The polysilicon is etched back to the planesurface. Using a mask (not shown), the polysilicon is recessed byetching to reach the top of the polysilicon lining the bottom of thetrench. The original gate oxide can be removed and a new oxide layergrown. The dielectric layer at the bottom of the top gate (gate-1) willbe relatively thin and this can be increased with additional oxidedepositions and planarization prior to gate-1 polysilicon.

In FIG. 10D, Gate-1 polysilicon 1080 is deposited and planarized. Thepolysilicon for both gates can be recessed to reduce capacitance. Theremaining dielectric and metal layers, including back metal, can beadded by conventional means to achieve the structure depicted in FIG.9A.

FIGS. 11A and 11B show cross section views of two TG-LDMOS structureswherein a charge-balancing technique is used to improve the breakdownvoltage in accordance with another embodiment of the invention. As shownin FIG. 11A, a p− type region 1110 extends laterally in the n− type LDDdrift region 1120 between the trench and the drain. The laterallyextending p− type region 1110 may have a fixed or graded dopingconcentration. The laterally-extending p− type region results in a moreuniform electric field in the LDD drift region thus improving the devicebreakdown voltage.

In alternate embodiments, the charge balance structure 1110 can beconfigured in parallel stripes and can be either floating orelectrically connected to the drain terminal 1130. They can also bepositioned on the surface (the easiest embodiment to manufacture).Alternatively, floating charge balance junctions can be arranged asislands dispersed within the body of the LDD region. The charge balancestructures allow the LDD structure 1120 to have higher dopingconcentration and thus lower resistance. These charge balance techniquescan be integrated with the source shield structure 1140 as shown in FIG.11B, with a dual gate structure, or with other TG-LDMOS structures toimprove the breakdown voltage.

FIGS. 12A and 13A show cross section views of TG-LDMOS structures havinga source-substrate via 1210 and drain-substrate via 1310, respectively,in accordance with other embodiments of the invention. The two viastructures are substantially similar except that in the source-substratevia structure 1210, the back side 1220 is a source coupled to a p+substrate 1230, and in the drain-substrate via structure 1310, the backside 1320 is a drain coupled to a n+ substrate 1330. Thesource-substrate via 1210 and drain-substrate via 1310 are used toreduce the source and drain resistance by replacing the relatively highresistance p+ sinker used for connection to the substrate with a trenchfilled with highly conductive material such as tungsten or in situ dopedpolysilicon. They also allow the surface area consumed by the substrateconnection to be reduced.

Further, the source-to-substrate 1210 and drain-to-substrate 1310connections allow monolithic integration of the TG-LDMOS with othercomponents such as additional DMOS for High Side/Low Side monolithicintegrated half bridge. They also can be used for chip scale packaging(CSP) where it is desirable to bump a driver onto the TG-LDMOS.

FIGS. 12B and 13B show alternate embodiments wherein the connection tothe substrate is further facilitated by a p+ layer 1240 formed aroundthe source-substrate via 1210 and a n+ layer 1340 formed around thedrain-substrate via 1310, respectively. The highly doped p+ 1240 and n+1340 layers may be formed by implanting dopants into the trenchsidewall. In an alternate embodiment, an oxide-lined polysilicon-filledtrench is used for simplicity.

The source-substrate connection and drain-substrate connection may beintegrated with any TG-LDMOS structure. As an example, FIGS. 12C and 13Cshow integration of these connections with the source-shield structureof FIG. 7.

Typically, a connection to the source from a package pin is made througha bond wire. But these bond wires add inductance that may degradeperformance. The source-to-substrate via 1210 allows a connection to thesource to be made through the back metal 1220, thus reducing thisinductance and source-series resistance.

These vias may be manufactured using one or more of several techniques.For example, the vias may be etched chemically or mechanically, by laserdrilling, micromachining, or other technique. The vias may then befilled or plated with a conductive material, such as metal. The vias maybe insulated or not, depending on the exact configuration of substrate,epitaxial, and other diffusions and implant material.

FIG. 14 is a cross section view illustrating how the source-substratevia 1410 can be advantageously used to obtain a smaller cell pitch.Similar advantage is obtained by the drain-substrate connection. In FIG.14, the source-substrate via 1410 is used only in the peripheral cell1420 to provide the source-to-substrate connection. Surface sourceinterconnections 1430 are used to interconnect to source regions 1440within the central half-cells 1450. By using such structure, there is noneed to have a trench source connection (or lateral diffusion “sinker”)in each unit cell. Thus, the pitch of the cell can be substantiallyreduced. It is to be understood, that although in FIG. 14 only twocentral half-cells 1450 are shown between the peripheral cells 1420, inpractice, many more central half-cells 1450 are present.

Any two or more of the different structural features illustrated inFIGS. 7, 9A, 11, 12A, and 13A may be combined together depending on thedesired device characteristics and design goals. A number of differentpossibilities are shown in FIGS. 15-19. Some of these Figures alsoillustrate variations in implementation of the basic conceptsillustrated in one of more of FIGS. 7, 9A, 11, 12A, and 13A. Many othervariations and combinations would be obvious to one of ordinary skill inthis art in view of this disclosure.

FIG. 15 shows one technique for interconnecting the source-shield 1510to the source terminal 1520. The source-shield 1510 is extendedlaterally along the bottom of the trench and then vertically to an upperportion of the trench where it is electrically connected to the sourceelectrode 1520. FIG. 16 shows the combination of the dual-gate structuredepicted in FIG. 9A with the source to substrate connection techniquedepicted in FIG. 12A.

FIG. 17 shows the dual-gate structure of FIG. 9A in combination with thecharge balance technique of FIG. 11. FIG. 18 shows a variation of thedual-gate structure wherein the lower gate (Gate-2) 1820 does not extendvertically parallel to the upper gate 1810 (although connection toGate-2 is provided in a third dimension), in combination with the chargebalance technique of FIG. 11. By using charge-balancing techniques incombination with the dual-gate or source-shield techniques, asignificantly greater breakdown voltage is achieved.

FIG. 19 shows the same variation of the dual-gate structure depicted inFIG. 18 in combination with an n+ drain sinker 1910. In anotherembodiment, the n+ drain sinker 1910 in FIG. 19 may be replaced with thedrain-substrate via 1310 shown in FIG. 13A. Note that the dual-gatestructure shown in FIGS. 12 and 13 are easier to manufacture than thestructure shown in FIG. 9A.

In the different embodiments described above, it is important to obtainhigh quality uniform insulating layers in the trench area. The insulatorat the corners of a trench typically thinner than other areas because ofdeposition difficulties (oxide grows faster on a planar surface than ona curved surface), and film stress at the silicon-oxide interface at thecorners (concave or convex) is greater. The combination of film stressand thinner oxide lead to less resistance to high electric fields andthus higher leakage current. Use of high-k dielectric can substantiallyreduces the leakage current. A combination of thermally grown SiO2 andnitride may be used to overcome the leakage problem. Alternatively, athin high quality high-k dielectric may be used either alone or incombination with, for example, an under-layer of thermally grown oxide.Further, the high-k dielectric may be used only for the gate insulatorwhere thin oxide (e.g., <100 Å) is used for greater transconductance(gm).

The various improvements described herein enable maintaining of theadvantages of the LDMOS structure (e.g., better linearity), whileincreasing the RF power gain and the device breakdown voltage. The DCdynamic losses in a high voltage switching diode translates into thedevice rise and fall times which in turn are proportional to the Gate toDrain capacitance (Cgd or Qgd, i.e., the Miller capacitance). By greatlyreducing Cgd, the rise and fall times are greatly reduced and hence thedynamic losses are greatly reduced. Thus, the dramatic reduction inparasitic capacitance allows safer operation even at fast switching andachieves higher efficiencies at low currents and higher voltages.

The above description of exemplary embodiments of the invention has beenpresented for the purposes of illustration and description. It is notintended to be exhaustive or to limit the invention to the precise formdescribed, and many modifications and variations are possible in lightof the teaching above. The embodiments were chosen and described inorder to best explain the principles of the invention and its practicalapplications to thereby enable others skilled in the art to best utilizethe invention in various embodiments and with various modifications asare suited to the particular use contemplated.

1. An apparatus, comprising: a first silicon region of a firstconductivity type, the first silicon region having a surface; agate-trench region extending from the surface of the first siliconregion into the first silicon region, the gate trench region comprising:a source-shield region comprising a first conductive region; a gateregion comprising a second conductive region and between the surface ofthe first silicon region and the source-shield region, the gate-trenchregion having an asymmetric insulating layer along two of its opposingsidewalls; a source region comprising a dopant region of a secondconductivity type, the dopant region laterally extending along one sideof the gate trench region and contacting a source electrode; and alightly-doped drain region of the second conductivity type laterallyextending below and along an opposing side of the one side of the gatetrench region and contacting a drain electrode.
 2. The apparatus ofclaim 1, wherein the source-shield region is between the gate region andthe lightly-doped drain region.
 3. The apparatus of claim 1, wherein thesource-shield region is a polysilicon region.
 4. The apparatus of claim1, wherein the source-shield region and gate regions are polysiliconregions.
 5. The apparatus of claim 1, wherein the lightly doped drainregion partially extends along a first sidewall of the gate trench suchthat a channel region along the first sidewall between the source regionand the lightly doped drain region extends along the vertical dimension.6. The apparatus of claim 1, further comprising: a charge-balance regionof the first conductivity type, the charge-balance region in thelightly-doped drain region.
 7. The apparatus of claim 1, wherein thefirst silicon region is an epitaxial layer formed on a substrate, theMOSFET further comprising: a source-substrate via coupling the source tothe substrate.
 8. The apparatus of claim 1, wherein the first siliconregion is an epitaxial layer formed on a substrate, the MOSFET furthercomprising: a drain-substrate via coupling the source to the substrate.9. An apparatus, comprising: a first silicon region of a firstconductivity type, the first silicon region having a surface; agate-trench region extending from the surface of the first siliconregion into the first silicon region, the gate trench region comprising:a first gate region comprising a first conductive region; a second gateregion comprising a second conductive region and between the surface ofthe first silicon region and the first gate region, the gate-trenchregion having an asymmetric insulating layer along two of its opposingsidewalls; a source region comprising a dopant region of a secondconductivity type, the dopant region laterally extending along one sideof the gate trench region and contacting a source electrode; and alightly-doped drain region of the second conductivity type laterallyextending below and along an opposing side of the one side of the gatetrench region and contacting a drain electrode.
 10. The apparatus ofclaim 9, wherein the first gate region is between the second gate regionand the lightly-doped drain region.
 11. The apparatus of claim 9,wherein the first and second gate regions are polysilicon regions. 12.The apparatus of claim 9, wherein the lightly doped drain regionpartially extends along a first sidewall of the gate trench such that achannel region along the first sidewall between the source region andthe lightly doped drain region extends along the vertical dimension. 13.The apparatus of claim 9, further comprising: a charge-balance region ofthe first conductivity type, the charge-balance region in thelightly-doped drain region.
 14. The apparatus of claim 9, wherein thefirst silicon region is an epitaxial layer formed on a substrate, theMOSFET further comprising: a source-substrate via coupling the source tothe substrate.
 15. The apparatus of claim 9, wherein the first siliconregion is an epitaxial layer formed on a substrate, the MOSFET furthercomprising: a drain-substrate via coupling the source to the substrate.16. An apparatus, comprising: a first silicon region of a firstconductivity type, the first silicon region having a surface; agate-trench region extending from the surface of the first siliconregion into the first silicon region, the gate trench region including agate region comprising a conductive region, the gate-trench region alsoincluding an asymmetric insulating layer along two of its opposingsidewalls; a source region comprising a dopant region of a secondconductivity type, the dopant region laterally extending along one sideof the gate trench region and contacting a source electrode; and alightly-doped drain region of the second conductivity type laterallyextending below and along an opposing side of the one side of the gatetrench region and contacting a drain electrode, the lightly-doped drainregion comprising a charge-balance region of the first conductivitytype.
 17. The apparatus of claim 16, wherein the charge-balance regionis between the gate-trench region and the drain electrode.
 18. Theapparatus of claim 17, wherein the first silicon region is an epitaxiallayer formed on a substrate, the MOSFET further comprising: asource-substrate via coupling the source to the substrate.
 19. Theapparatus of claim 17, wherein the first silicon region is an epitaxiallayer formed on a substrate, the MOSFET further comprising: adrain-substrate via coupling the source to the substrate.
 20. Theapparatus of claim 17, wherein the lightly doped drain region partiallyextends along a first sidewall of the gate trench such that a channelregion along the first sidewall between the source region and thelightly doped drain region extends along the vertical dimension.